1. Field of the Invention
The invention relates to a semiconductor device and, more particularly, to a semiconductor device with substrate-triggered electrostatic discharge (ESD) protection.
2. Description of the Prior Art
With the continued scaling down of semiconductor integrated circuit (IC) devices, the present trend is moving towards production of semiconductor integrated circuits having very small sizes in the advanced sub-quarter-micron CMOS technologies. It is consequently increasingly important to build electrostatic discharge (ESD) protection circuits on the chip to protect the devices and circuits of the IC against ESD-related damage. The ESD robustness of commercial IC products is generally needed to be higher than 2 kV in the human-body-model (HBM) ESD stress. While withstanding ESD overstress, it is desired that the on-chip ESD protection circuits have relatively small dimensional requirements to save silicon area. With respect to this issue, heat dissipation issues become paramount. In the present, the efficiency and performance of the substrate-trigger ESD protection circuits is better than other type ESD protection circuits.
Please refer to FIG. 1. FIG. 1 is schematic diagram of a prior art semiconductor device 30 with substrate-triggered ESD technique. The semiconductor device 30 is disclosed in U.S. Pat. No. 6,639,283 “Semiconductor device with substrate-triggered ESD protection” by Kei-Kang et al. The semiconductor device 30 has a guard ring 31 and a MOS transistor array 32. The MOS transistor array 32 has a plurality of MOS transistors 321, a plurality of fingers 322 constituted by the gates of the MOS transistors 321, and a plurality of substrate-triggered areas 323 between the fingers 322. As shown in FIG. 2, a plurality of N+ diffusion areas and a plurality of P+ diffusion areas are formed on a substrate 40. The N+ diffusion areas serve as the source and the drain of the MOS transistors 321 shown in FIG. 1, respectively. The periphery P+ diffusion area serves as the guard ring 31 shown in FIG. 1. The N+ diffusion areas and the substrate 40 form the parasitic bipolar junction transistors (parasitic BJTs) 43 and 44. Thus, the junction between the base and the emitter of each parasitic BJT 43 and 44 is forward biased by the ESD pulse, such as of a human-body mode (HBM), in order to trigger the parasitic BJTs 43 and 44 into an active region. Thus, the MOS transistor array 32 can be protected. The semiconductor device 30 has a plurality of P+ diffusion areas 41 and a plurality of isolation portions 42. Each of the isolation portions 42 can be a shallow trench isolation (STI) portion for separating the P+ diffusion areas 41 from the N+ diffusion areas. Thus, when the ESD event occurs, the trigger current Itrig flows through the P+ diffusion areas 41 to the substrate 40, and then the bases of parasitic BJTs 43 and 44 are biased. Accordingly, the parasitic BJTs 43 and 44 can be triggered simultaneously to discharge the electrostatic charge.
However, since three substrate-triggered areas 323 (as shown in FIG. 1) have to be provided for four fingers 322, these substrate-triggered areas 323 may increase the area of the circuit layout. The manufacturing cost of the semiconductor device 30 is thus increased.
Please refer to FIG. 3, Kei-Kang et al. discloses another prior art semiconductor device 50 with substrate-triggered ESD protection technique. The semiconductor device 5 has a guard ring 51, a first MOS transistor array 52, a second MOS transistor array 53, a substrate-triggered portion 54 and an isolation portion 55. The first MOS transistor array 52, the second MOS transistor array 53, the substrate-triggered portion 54, and the isolation portion 55 are formed in a region surrounded by the guard ring 51. The substrate-triggered portion 54 is located between the first MOS transistor array 52 and the second MOS transistor array 53. In addition, the isolation portion 55 is formed among the guard ring 51, the first MOS transistor array 52, the second MOS transistor array 53, and the substrate-triggered portion 54 so as to separate these regions.
Please refer to FIGS. 4–5. FIG. 4 is a cross-sectional diagram of the semiconductor device 50 along the dashed line 4–4′ shown in FIG. 3. FIG. 5 is a cross-sectional diagram of the semiconductor device 50 along the dashed line 5–5′ shown in FIG. 3. The guard ring 51 is formed on a P+ diffusion area 61 of a substrate 60. In addition, the first MOS transistor array 52, the second MOS transistor array 53, the substrate-triggered portion 54 and the isolation portion 55 can be an N+ diffusion area 62, an N+ diffusion area 63, a P+ diffusion area 64, and a shallow trench isolation (STI) portion 65 formed on the substrate 60, respectively. It is obvious from FIG. 4 that the shallow trench isolation portion 65 isolates the N+ diffusion area 62, the N+ diffusion area 63, and the P+ diffusion area 64 from one another.
As stated above, the first MOS transistor array 52 and the second MOS transistor array 53 has a parasitic BJT 521 (as shown in FIG. 6) respectively. When the ESD event occurs, the trigger current Itrig can flow through the P+ diffusion area 64 to the P+ diffusion area 61 serving as the guard ring 51, so as to produce a voltage drop. The voltage drop is the product of the trigger current Itrig and the substrate resistor Rsub and is capable of forward-biasing the base-emitter junctions of the parasitic BJTs 521 into active states, so as to enable the parasitic BJTs 521 to discharge the electrostatic charge.
However, because the distance between the guard ring 51 and the end of the substrate-triggered portion 54 is less than the distance between the guard ring 51 and the center of the substrate-triggered portion 54, the resistance between the guard ring 51 and the end of the substrate-triggered portion 54 is less than the resistance between the guard ring 51 and the center of the substrate-triggered portion 54. Therefore, the trigger current Itrig2 (as shown in FIG. 5) should be greater than the trigger current Itrig1 (as shown in FIG. 4), where Itrig=Itrig1+Itrig2. Hence, most of the trigger current Itrig passes from the two ends of the substrate-triggered portion 54 to the guard ring 51. The base-emitter junctions of the parasitic BJTs 521, thus, are hard to be forward-biased, and the ESD performance of the semiconductor device 50 is undesired.
Please refer to FIG. 7, Kei-Kang et al. discloses another prior art semiconductor device 70 with substrate-triggered ESD protection technique. The semiconductor device 70 further comprises a first N-well 56 and a second N-well 57. The first N-well 56 and the second N-well 57 are formed between the first MOS transistor array 52 and the second MOS transistor array 53, and are located near two ends of the substrate-triggered portion 54, respectively. Since the first N-well 56 and the second N-well 57 are N diffusion areas that are deeply diffused into the substrate, and the substrate-triggered portion 54 is a P+ diffusion area, when the ESD event occurs, the trigger current flows from the substrate-triggered portion 54 to the substrate. At this time, due to the blocking effects of the first N-well 56 and the second N-well 57, the trigger current components toward the first N-well 56 and the second N-well 57 decrease. Consequently, the trigger current components toward the first MOS transistor array 52 and the second MOS transistor array 53 correspondingly increase. In this case, the trigger current can more easily bias the bases of the parasitic BJTs in the first MOS transistor array 52 and the second MOS transistor array 53.
In contrast with the semiconductor devices 30 and 50, even through the semiconductor device 70 had been improved, the semiconductor device 70 has a drawback that the first N-well 56 and the second N-well 57 are too short to effectively block the trigger current components toward the first N-well 56 and the second N-well 57.